LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AC_D is ---
port (
		LOAD_D : IN STD_LOGIC; ---
		clk : IN STD_LOGIC;
		Data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		D : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ---
);
end AC_D; ---

ARCHITECTURE accu OF AC_D IS ---

BEGIN

  PROCESS(clk,LOAD_D,data_in) ---
   BEGIN
	IF clk'event AND clk = '1' THEN 
		IF LOAD_D = '1' THEN  ---
		D <= Data_in; ---
		END IF;
	END IF;
	
  END PROCESS;

END accu;